Announcing the RZ/Five General-Purpose MPU with 64-Bit RISC-V CPU Core for the First Time in the World | Renesas
🟦 Developing Renesas RISC-V Microcontrollers Ahead of the World
Renesas Electronics has begun shipping samples of 64-bit microcontrollers that use RISC-V (Risk Five). Renesas’ first microcontroller to use RISC-V was an IP designed by Taiwan’s Andean Technology Co., Ltd. as the CPU core. This is a general-purpose microcontroller “RZ/Five” that is scheduled to start mass production in July 2022. It is pin compatible with the RZ series of conventional ARM CPU cores to facilitate development in the conventional environment. In the past, Renesas had been behind the competition in launching general-purpose microcontrollers that used ARM, and had indicated its intention to accelerate the market launch of products using RISC-V. In April 2021, we announced a collaboration with SiFive, a U.S.-based retailer of RISC-V IP, for automotive applications.
RISC-V (Risk Five)
RISC-V is an open-source instruction set architecture (ISA) developed by the University of California, Berkeley since 2010. Because it is open source, it is open to the public free of charge, and anyone can use it for design free of charge. Since ISA is an instruction set of basic specifications, performance depends on detailed design, but it is generally said that RISC-V’s strengths are power efficiency and high security functions. By 2025, the adoption rate of RISC-V is expected to reach 28% for IoT terminals, 12% for industrial equipment, and 10% for automobiles.
In terms of CPU IP, ARM maintains a dominant market share, and is also aiming to enter IoT starting from smartphones. RISC-V, which is open source, has become a competitive axis for ARM due to its increasing degree of freedom in IP design.
🟦 Benefits of being open source
The instruction set architecture of the current mainstay CPU is Intel’s “x86” for PCs and servers, and the arm for smartphones. RISC-V is gaining traction because it is open source and does not belong to any company. There are two reasons for this: Nvidia’s planned acquisition of ARM and the economic friction between the U.S. and China.
The possibility that ARM’s ISA and IP could fall into the hands of certain companies in a neutral position has raised the alarm of rival companies. In addition, due to the economic friction between the United States and China, semiconductors have been strongly affected by export restrictions in each country. It is hoped that RISC-V, which is independent of any specific company, has the potential to reduce the risk of exposure to national regulations.
Due to the demand for the RISC-V, Renesas’ RISC-V MCUs are targeted at customers in the Chinese market. Renesas procured IP from the Andes, but in the future there are plans to launch its own IP and software development tools.
Renesas has developed a general-purpose MPU with a RISC-V CPU core that reduces the risk of exposure to regulations in each country with an awareness of the Chinese market.
Renesas, which has a fabright strategy, thinks it’s good to increase design power without being tied to a specific IP.