TSMC is advancing “CoPoS” (Chip-on-Panel-on-Substrate), an advanced packaging technology for large AI and HPC chips. Rather than the conventional circular 12-inch wafer, CoPoS uses a 310x310mm square panel, aiming to significantly improve packaging efficiency for large-die chips. At TSMC’s shareholder meeting in June 2026, Chairman C.C. Wei laid out the company’s first roadmap: equipment validation in 2026, pilot production in 2027, and mass production starting in the second half of 2028. However, multiple media reports, including TrendForce and XenoSpectrum, confirm that full commercialization of glass-core substrates is unlikely before 2030.
What This Article Covers
- How CoPoS technology works and its roadmap toward mass production
- The specific technical barriers facing glass substrates
- What TSMC’s chairman’s comments reveal about the actual state of development
Overview
Using glass substrates, TSMC has, for the first time, published joint validation data with Ibiden and Innolux showing that packaging warpage can be improved by 16%, effective thermal expansion coefficient reduced by 19%, and effective elastic modulus increased by 31% compared to conventional materials. However, these are simulation results, and demonstration at mass-production scale is still ahead.
Details
The following points were confirmed through multiple independent media reports, including TrendForce and XenoSpectrum.
- TSMC is advancing CoPoS (310x310mm panel format), planning equipment validation in 2026, pilot production in 2027, and mass production starting in the second half of 2028 — but full commercialization of glass-core substrates isn’t expected before 2030
- The biggest technical barrier is substrate warpage, where thermal stress-induced warping directly affects yield as panel sizes grow
- TGV (Through-Glass Via) technology also remains immature, facing multiple challenges: inconsistent via dimensions from laser energy fluctuations, microscopic cracks during drilling, and difficulty achieving effective metallization in sub-10-micron vias
- TSMC Chairman C.C. Wei told shareholders there are “no shortcuts,” and that reaching mass-production scale will take another two to three years
- In a joint validation between TSMC, Ibiden, and Innolux, simulation data showed glass substrates improving packaging warpage by 16%, reducing effective thermal expansion coefficient by 19%, and increasing effective elastic modulus by 31% — the first such data made public
Industry Impact
Next-generation packaging technologies like CoPoS are a critical enabling technology for the implementation efficiency of large AI and HPC chips. TSMC’s chairman himself stating there are “no shortcuts” is notable as a frank acknowledgment of the scale of remaining technical challenges, against industry expectations that may have run ahead of reality. The prospect of full glass substrate commercialization slipping past 2030 is a data point worth factoring into the broader timeline for large AI chip packaging technology roadmaps.
Relevance to Japan
This technical validation includes Japan’s major substrate maker Ibiden. The practical realization of glass substrate and TGV technology is likely to depend significantly on the technical capabilities of Japanese companies strong in substrate materials and manufacturing equipment, making progress on overcoming these technical barriers directly relevant to business opportunities for Japanese supply chain companies.
What to Watch Next
- Progress on improving TGV technology (drilling precision, metallization)
- How this compares to competing glass substrate development at Intel and Samsung
- Whether mass production begins on schedule in the second half of 2028
- Specific validation data on cost reduction
Summary
TSMC’s next-generation packaging technology, CoPoS, is targeting mass production in the second half of 2028, but full commercialization of glass-core substrates isn’t expected before 2030 due to substrate warpage and TGV technical challenges. TSMC’s own chairman has acknowledged there are “no shortcuts,” and what’s next is to track progress on overcoming these technical barriers and the response from supply chain companies, including those in Japan.
