AMD’s CDNA 5 architecture combines a 2nm process, chiplets and HBM4 for its next generation of data-center AI accelerators. Instinct MI455X is positioned to compete with NVIDIA’s Vera Rubin generation by addressing compute, memory and interconnect together.
A chiplet-based design
CDNA 5 separates accelerator complex dies from fabric and cache dies. Splitting compute, cache and connectivity can improve yield and provide more flexibility than building every function into one very large die. AMD presents the architecture as an early GPU design using TSMC’s 2nm process.
HBM4 for larger models
Instinct MI455X uses HBM4 to keep model weights and intermediate data close to the accelerator at high bandwidth. As AI models grow, memory capacity and bandwidth can limit performance as much as arithmetic throughput. Integrating HBM4 with a chiplet system is therefore central to the design.
Compare systems, not only GPUs
AMD claims advantages over Vera Rubin NVL72 in FP4 performance, HBM capacity, bandwidth, scale-out bandwidth and token cost. Those results depend on configuration, software and benchmark conditions. Data-center buyers should evaluate complete racks and operating cost rather than a single peak metric.
Takeaway
CDNA 5 targets the real bottlenecks of AI infrastructure: memory, connectivity and manufacturability as well as compute. AMD’s success against NVIDIA will depend on MI455X availability, ROCm adoption and production deployments.
Source: AMD Instinct MI400 product page (accessed August 10, 2026).
