Cadence and Samsung are collaborating to enhance SoC, 3D-IC, and chiplet designs for AI data centers and automotive applications to accelerate the development of next-generation semiconductors.
🟦 Cadence and Samsung strengthen design collaboration
Cadence and Samsung announced enhanced design tools and IP for modern manufacturing process nodes. This expansion of the partnership will enable the rapid development of high-performance, low-power chips required in the AI, automotive, and communications sectors.
- Cadence Expands Interface and Memory IP Offerings for Samsung’s SF4X, SF5A and SF2P Nodes
- Joint certification and development of a fully digital design flow and AI-assisted tool for the SF2P process
- GPU acceleration is introduced for power, thermal, and warpage analysis required for 3D-ICs to improve design accuracy
In addition, cooperation is underway in several other areas, including support for the latest IP such as LPDDR6, PCIe 6.0, and CXL 3.2, the transition of analog IP to 2nm, and the RF chip design flow.
🟦 Background to the need to accelerate next-generation design
The background to this strengthening of the alliance is an industry trend that requires semiconductors that achieve both processing performance and energy efficiency in fields such as AI, HPC (high-performance computing), and ADAS (advanced driver assistance systems).
We live in an era where EDA tools and IP are indispensable for increasingly complex designs such as advanced process nodes, 3D-ICs, and chiplets. The collaboration between Cadence and Samsung is a practical and strategic move to address these needs and shorten the time to silicon implementation.
🟦 Summary
The expansion of the partnership between Cadence and Samsung is an important step in achieving both time savings and performance optimization in advanced chip design. As a stepping stone for solving design issues in the AI era, future results will attract attention.
Competitors Synopsys and TSMC have developed similar partner strategies, and vertically integrated collaboration between EDA and foundries will become increasingly important in the future.
